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NXP Semiconductors /LPC5410x /DMA /CTLSTAT21

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Interpret as CTLSTAT21

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NO_EFFECT)VALIDPENDING 0 (RESERVED)RESERVED 0 (NOT_TRIGGERED)TRIG 0 (RESERVED)RESERVED

TRIG=NOT_TRIGGERED, VALIDPENDING=NO_EFFECT

Description

Control and status register for DMA channel 0.

Fields

VALIDPENDING

Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel.

0 (NO_EFFECT): No effect. No effect on DMA operation.

1 (VALID_PENDING): Valid pending.
RESERVED

Reserved. Read value is undefined, only zero should be written.
TRIG

Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1.

0 (NOT_TRIGGERED): Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out.

1 (TRIGGERED): Triggered. The trigger for this DMA channel is set. DMA operations will be carried out.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data